The development of new techniques and processing methods for manipulating, organizing and integrating matter on the scale of nanometers is critically important to continued advances in the field of nanotechnology. These advances are expected to widely impact fundamental and applied technology areas ranging from materials science and physics to applied engineering and biotechnology. Furthermore, progress in the field of nanotechnology is anticipated to enable a new class of devices based on nanoscale electrical, mechanical, magnetic and/or optical elements. Such nanotechnology enabled devices are predicted to revolutionize an incredibly diverse range of fields including sensing, electronics, optoelectronics, photovoltaics, fluidics, quantum computing, biotechnology and medicine.
Fabrication of devices with elements having nanoscale dimensions is not merely a natural extension of the concept of miniaturization, but a fundamentally different regime in which physical and chemical behavior substantially deviates from larger scale systems. The behavior of nanoscale assemblies of many materials is greatly influenced by their large interfacial volume fractions and quantum mechanical effects arising from electronic confinement. The ability to make structures having well-defined features on the scale of nanometers has opened up the possibility of making devices based on these properties and processes only occurring in the nanoscale domain. For example, there is currently great interest in developing useful functional devices based on controlled single-electron tunneling, Coulomb blockage and quantum size effects.
Single electron tunneling (SET) transistors are one class of nanoscale devices of particular interest due to their very small dimensions and low power dissipation, which make them ideal candidates for making dense integrated electronic circuits, such as logic and memory circuits. A SET transistor is a three terminal device comprising an active element, commonly referred to as a Coulomb island, coupled to source and drain electrodes via high resistance tunnel junctions and coupled to a gate electrode that it is capable of electrostatically influencing electrons transported between source and drain electrodes. The presence of the tunnel junctions prevents mixing of the electronic states of electrons on the Coulomb island with external states, thereby achieving substantial electronic confinement and isolation. The energy of an electron must be equal the Coulomb energy (e2/2C) for it to be transported onto the Coulomb island and charge passes through the Coulomb island in quantized units. In typical operation, when both the gate and bias voltage between source and drain electrodes are equal to zero, electrons do not have enough energy to enter the Coulomb island and charge does not flow. As the bias voltage is increased, however, the system reaches the Coulomb energy and electrons flow between the source and drain electrodes. In metallic and superconducting SET transistors where the charging energy is significantly larger than the confinement energy, the current that flows from source to drain electrodes is a periodic function of the gate voltage. On the other hand, the current that flows from source to drain electrodes is not a strictly periodic function of the gate voltage in semiconducting SET transistors where the charging energy is on the same order of magnitude as the confinement energy.
Continued advancement of useful nanotechnology based devices, such as SET transistors, is critically dependent on the developing commercially practicable methods of fabricating sub-micrometer sized structures from a range of materials including metals, semiconductors, superconductors and dielectrics. Recent advances in photolithography have extended the applicability of these techniques to the fabrication of structures having submicron physical dimensions. For example, nanolithographic techniques, such as deep UV projection mode lithography, soft X-ray lithography, electron beam lithography and scanning probe methods, have been successfully employed to fabricate structures with features on the order of 10s to 100s of nanometers. These developments have enabled fabrication of a wide range of functional devices having integrated active nanoscale elements including metallic, superconducting and semiconducting SETs; quantum dot optical detection systems; nanowire, nanocrystal and thin film based transistors and photovoltaic devices; nanoelectromechanical systems; and nanofluidic systems.
Despite these advances, techniques capable of fabricating structures having even smaller physical dimensions are needed to enable many useful nanotechnology based devices. For example, a significant problem of SET transistors fabricated using photolithography methods and having a Coulomb island with physical dimensions equal to or greater than about 20 nanometers is that they must be cooled down to low temperatures to achieve useful device performance. The fundamental problem with these devices is that the Coulomb blockage is washed out via thermal fluctuations if the energy that is necessary to add an electron to the Coulomb island is smaller than the characteristic thermal energy (kBT). Therefore, to achieve SETs exhibiting good device performance at room temperature requires a reduction in the scale of their physical dimensions to about ˜10 nm or less to access good device performance. This requirement occurs because the relevant internal energy scale must be much larger than the energy of thermal fluctuations. In SET transistors, for example, the relevant energy scale is the Coulomb charging energy, EC=e2/2C=e2/4πε0D. Here C is the total electric capacitance of the active element of the device (so-called Coulomb island), which is assumed to be spherical, D is the diameter of the Coulomb island, ε0 is the permittivity of free space. The condition for the room temperature operation is written as EC>>Eth=kBT=4·10−21 J (here T=293K is the “room temperature”). This requirement translates into a size restriction for the Coulomb island D<5.8 nm (assuming the condition EC=10Eth). Fabrication of electronic devices and device components with dimensions below 10 nm, however, remains very challenging.
It will be appreciated from the foregoing that there is currently a need for new powerful nanofabrication techniques capable of producing metallic and/or semiconductor structures having physical dimensions below 10 nm. It is therefore a goal of the present invention to provide methods for generating sub 10 nanometer structures with high resolution. Further it is a goal of the present invention to provide methods of making and integrating active elements having sub-10 nanometer dimensions in functional devices, including SET transistors and integrated circuits comprising interconnected SETs.